1. Field of the Invention
The present invention relates to a level shifter used in a driver circuit for a display device, and in particular, to a level shifter used in a driver circuit for a display device, the driver circuit using thin film transistors (hereinafter referred to as TFTs) formed on an insulator. It is to be noted that, in this specification, a display device means one used as an LCD (a liquid crystal display), an OLED (an organic EL display), or the like.
2. Description of the Related Art
Recently, semiconductor microfabrication technology has been advanced, which is accompanied by miniaturization of LSIs. This results in more active application of such LSIs to small-sized apparatus such as personal digital assistants, which requires lower power consumption of such LSIs. Today, LSIs driven at low power supply voltage such as 3.3 V are mainly used.
On the other hand, with regard to LCDs (liquid crystal displays) the demands for which are remarkably increasing these days in the field of personal digital assistants, monitors for computers, and the like, liquid crystal is often driven by a signal having the voltage amplitude of 10 V-20 V. Therefore, a driver circuit of such liquid crystal includes at least a circuit portion driven by high power supply voltage.
Accordingly, it is indispensable that a controller LSI using the abovementioned LSI which is driven at low power supply voltage is connected to a circuit for driving the liquid crystal which is driven at high power supply voltage through a level shifter for changing the amplitude voltage of the signal.
FIGS. 12A and 12B illustrate circuit diagrams of commonly used level shifters. It is to be noted that in this specification each power supply potential is denoted as VDD# (# is a numeral) or GND. Here, VDD1, VDD2, VDD3, and VDD4 are used wherein VDD4 less than VDD3 less than GND less than VDD1 less than VDD2. For the sake of simplicity, GND is fixed to 0 V.
The level shifter illustrated in FIG. 12A converts an input signal having the voltage amplitude of GNDxe2x88x92VDD1 into an output signal having the voltage amplitude of GNDxe2x88x92VDD2. More specifically, the amplitude is converted by fixing the lower potential side and converting the potential at the higher potential side. The level shifter is structured as follows. Both of a source region of a first p-type TFT 1201 and a source region of a second p-type TFT 1202 are connected to the power supply VDD2. A drain region of the first p-type TFT 1201 is connected to a source region of a third p-type TFT 1203, and a drain region of the second p-type TFT 1202 is connected to a source region of a fourth p-type TFT 1204. A drain region of the third p-type TFT 1203 is connected to a drain region of a first N type thin film transistor (hereinafter referred to as an n-type TFT) and a gate electrode of the second p-type TFT 1202. A drain region of the fourth p-type TFT 1204 is connected to a drain region of a second n-type TFT 1206 and a gate electrode of the first p-type TFT 1201. Both of a source region of the first n-type TFT 1205 and a source region of the second n-type TFT 1206 are connected to GND (=0 V). An input signal (In) is input to a gate electrode of the third p-type TFT 1203 and a gate electrode of the first n-type TFT 1205. An inverted signal of the input signal (Inb) is input to a gate electrode of the fourth p-type TFT 1204 and a gate electrode of the second N-type TFT 1206. An output signal (Out) is taken out from the drain region of the fourth n-type TFT 1204. Here, an inverted output signal (Outb) can also be taken out from the drain region of the third p-type TFT 1203.
It is to be noted that, though there are n-type and p-type as the conductive types of a TFT, in this specification, in the case where the polarity of a TFT is not specifically limited, the conductive types are described as a first conductive type and a second conductive type. For example, when the first conductive type TFT is of the n-type, the second conductive type means the p-type. Conversely, when the first conductive type TFT is of the p-type, the second conductive type means the n-type.
Next, basic operation of the conventional level shifter is described. When an Hi signal is input as the input signal (In), the n-type TFT 1205 is in a conductive state while the p-type TFT 1203 is in a nonconductive state. Therefore, a signal having the potential of GND, that is, an Lo signal, is input to the gate electrode of the p-type TFT 1202, and the p-type TFT 1202 is in a conductive state. On the other hand, here, the inverted input signal (Inb) is an Lo signal. Therefore, the n-type TFT 1206 is in a nonconductive state while the p-type TFT 1204 is in a conductive state. Since both of the p-type TFTs 1202 and 1204 are in a conductive state, an Hi signal is outputted as the output signal (Out) with the potential of VDD2. It is to be noted that the p-type TFT 1201 is in a nonconductive state, which assures that the potential of the gate electrode of the p-type TFT 1202 is held at Lo=GND.
When the potential of the input signal (In) is Lo, since the level shifter illustrated in FIG. 12A is structured to be symmetrical, an Lo signal is outputted from the output terminal (Out) with the potential of GND, that is, 0 V.
In this way, an input signal having the voltage amplitude of GNDxe2x88x92VDD1 is converted into an output signal having the voltage amplitude of GNDxe2x88x92VDD2.
Next, the level shifter illustrated in FIG. 12B converts an input signal having the voltage amplitude of VDD3xe2x88x92GND into an output signal having the voltage amplitude of VDD4xe2x88x92GND. More specifically, the amplitude is converted by fixing the higher potential side and converting the potential at the lower potential side. The level shifter is structured as follows. Both of a source region of a first n-type thin film transistor (hereinafter referred to as an n-type TFT) 1211 and a source region of a second n-type TFT 1212 are connected to a power supply VDD4. A drain region of the first n-type TFT 1211 is connected to a source region of a third n-type TFT 1213, and a drain region of the second n-type TFT 1212 is connected to a source region of a fourth n-type TFT 1214. A drain region of the third n-type TFT 1213 is connected to a drain region of a first p-type thin film transistor (hereinafter referred to as a p-type TFT) 1215 and a gate electrode of the second n-type TFT 1212. A drain region of the fourth n-type TFT 1214 is connected to a drain region of a second p-type TFT 1216 and a gate electrode of the first n-type TFT 1211. Both of a source region of the first p-type TFT 1215 and a source region of the second p-type TFT 1216 are connected to GND (=0 V). An input signal (In) is input to a gate electrode of the third n-type TFT 1213 and a gate electrode of the first p-type TFT 1215. An inverted signal of the input signal (Inb) is input to a gate electrode of the fourth n-type TFT 1214 and a gate electrode of the second p-type TFT 1216. An output signal (Out) is taken out from the drain region of the fourth n-type TFT 1214. Here, an inverted output signal (Outb) can also be taken out from the drain region of the third n-type TFT 1213.
Next, basic operation of the conventional level shifter is described. When an Lo signal is input as the input signal (In), the p-type TFT 1215 is in a conductive state while the n-type TFT 1213 is in a nonconductive state. Therefore, a signal having the potential of GND, that is, an Hi signal, is input to the gate electrode of the n-type TFT 1212, and the n-type TFT 1212 is in a conductive state. On the other hand, here, the inverted input signal (Inb) is an Hi signal at this time. Therefore, the p-type TFT 1216 is in a nonconductive state while the n-type TFT 1214 is in a conductive state. Since both of the n-type TFTs 1212 and 1214 are in a conductive state, an Lo signal is outputted as the output signal (Out) with the potential of VDD4. It is to be noted that the n-type TFT 1211 is in a nonconductive state, which assures that the potential of the gate electrode of the n-type TFT 1212 is held at Hi=GND.
When the potential of the input signal (In) is Hi, since the level shifter illustrated in FIG. 12B is structured to be symmetrical, an Hi signal is outputted from the output terminal (Out) with the potential of GND, that is, 0 V.
In this way, an input signal having the voltage amplitude of VDD3xe2x88x92GND is converted into an output signal having the voltage amplitude of VDD4xe2x88x92GND.
A problem with regard to the level shifters illustrated in FIGS. 12A and 12B is now described. It is to be noted that, since the problem is common to the level shifters illustrated in FIGS. 12A and 12B, only the one illustrated in FIG. 12A is described by way of example. As described in the above, today, controller LSIs operating at 3.3 V are mainly used. Suppose the level shifter illustrated in FIG. 12A carries out conversion in case of VDD1=3 V and VDD2=10 V. When the amplitude of the input signal to the TFTs 1203, 1204, 1205, and 1206 is 3 V and the threshold voltage of the n-type TFTs 1205 and 1206 is 3 V, the level shifter is not expected to operate normally. More specifically, since, as the voltage amplitude before conversion becomes smaller, the gate-source voltage becomes less likely to be high enough to make the TFTs sufficiently conductive, normal operation becomes more difficult.
Accordingly, an object of the present invention is to provide a novel level shifter the normal operation of which can be guaranteed even in case a driver circuit is driven at lower power supply voltage, which is accompanied by a lower voltage amplitude of an input signal.
In order to solve the above problem, the present invention is structured as in the following.
In the conventional level shifter, an input signal is input to gate electrodes of TFTs 1203, 1204, 1205, and 1206 in FIG. 12A. When the voltage amplitude of the input signal becomes lower than the absolute values of the thresholds of the TFTs, gate-source voltage high enough to make the TFTs sufficiently conductive can not be obtained, which makes normal operation impossible.
Therefore, in a level shifter according to the present invention, the paths of the input signal are contrived to make the thresholds of the TFTs less liable to have the adverse effect even when the voltage amplitude of the input signal becomes lower. Further, in converting the voltage amplitude, by using a differential amplifier circuit which is a combination of a current mirror circuit and a differential circuit, high gain can be obtained.
The configuration of the level shifter of the present invention is disclosed hereinbelow.
According to the first aspect of this invention, a level shifter for converting a signal having a low voltage amplitude into a signal having a high voltage amplitude and for outputting the converted signal, comprising:
a current mirror circuit;
a differential circuit having the current mirror circuit as a load;
a first current source for supplying current to the differential circuit; and
first and second source follower circuits,
is characterized in that:
a first input signal is input through the first source follower circuit to the differential circuit; and
a second input signal is input through the second source follower circuit to the differential circuit.
According to a second aspect of the present invention, a level shifter for converting a signal having a low voltage amplitude into a signal having a high voltage amplitude and for outputting the converted signal, comprising:
a current mirror circuit;
a differential circuit having the current mirror circuit as a load;
a first current source for supplying current to the differential circuit;
first and second transistors, a gate electrode and a drain region of the first transistor being electrically connected to each other and a gate electrode and a drain region of the second transistor being electrically connected to each other; and
second and third current sources for supplying current to the first and second transistors, respectively,
is characterized in that:
a first input signal is input through the first transistor to the differential circuit; and
a second input signal is input through the second transistor to the differential circuit.
According to a third aspect of the present invention, a level shifter for converting a signal having a low voltage amplitude into a signal having a high voltage amplitude and for outputting the converted signal, comprising:
a current mirror circuit;
a differential circuit having the current mirror circuit as a load;
a first current source for supplying current to the differential circuit;
first and second transistors, a gate electrode and a drain region of the first transistor being electrically connected to each other and a gate electrode and a drain region of the second transistor being electrically connected to each other; and
second and third current sources for supplying current to the first and second transistors, respectively,
is characterized in that:
the differential circuit comprises third and fourth transistors;
a drain region of the first transistor and a gate electrode of the third transistor are electrically connected to each other;
a drain region of the second transistor and a gate electrode of the fourth transistor are electrically connected to each other;
a first input signal is input through the first transistor to the gate electrode of the third transistor; and
a second input signal is input through the second transistor to the gate electrode of the fourth transistor.
According to a fourth aspect of the present invention, a level shifter for converting a signal having a low voltage amplitude into a signal having a high voltage amplitude and for outputting the converted signal, comprising:
a first transistor of a first conductive type, a gate electrode and a drain region thereof being electrically connected to each other;
a second transistor of the first conductive type, a gate electrode and a drain region thereof being electrically connected to each other;
a differential circuit comprising a third transistor of the first conductive type and a fourth transistor of the first conductive type;
a current mirror circuit comprising a fifth transistor of a second conductive type and a sixth transistor of the second conductive type, a gate electrode and a drain region of the fifth transistor being connected to each other;
a seventh transistor of the first conductive type for electrically connecting the differential circuit and a first current source;
an eighth transistor of the second conductive type for electrically connecting the fifth transistor and a second current source;
a ninth transistor of the second conductive type for electrically connecting the sixth transistor and a third current source; and
a power supply portion for supplying potential to gate electrodes of the seventh, eighth, and ninth transistors,
is characterized in that:
a first input signal is input through the first transistor to a gate electrode of the third transistor; and
a second input signal is input through the second transistor to a gate electrode of the fourth transistor.
According to a fifth aspect of the present invention, a level shifter for converting a signal having a low voltage amplitude into a signal having a high voltage amplitude and for outputting the converted signal, comprising:
first and second current mirror circuits;
a differential circuit electrically connected to the first and second current mirror circuits;
a first current source for supplying current to the differential circuit; first and second transistors, a gate electrode and a drain region of the first transistor being electrically connected to each other and a gate electrode and a drain region of the second transistor being electrically connected to each other; and
second and third current sources for supplying current to the first and second transistors, respectively,
is characterized in that:
a first input signal is input through the first transistor to the differential circuit; and
a second input signal is input through the second transistor to the differential circuit.
According to a sixth aspect of the present invention, a level shifter for converting a signal having a low voltage amplitude into a signal having a high voltage amplitude and for outputting the converted signal, comprising:
first and second current mirror circuits;
a differential circuit electrically connected to the first and second current mirror circuits;
a first current source for supplying current to the differential circuit;
first and second transistors, a gate electrode and a drain region of the first transistor being electrically connected to each other and a gate electrode and a drain region of the second transistor being electrically connected to each other; and
second and third current sources for supplying current to the first and second transistors, respectively,
is characterized in that:
the differential circuit comprises third and fourth transistors;
a drain region of the first transistor and a gate electrode of the third transistor are electrically connected to each other;
a drain region of the second transistor and a gate electrode of the fourth transistor are electrically connected to each other;
a first input signal is input through the first transistor to the gate electrode of the third transistor; and
a second input signal is input through the second transistor to the gate electrode of the fourth transistor.
According to a seventh aspect of the present invention, a level shifter for converting a signal having a low voltage amplitude into a signal having a high voltage amplitude and for outputting the converted signal, comprising:
a current mirror circuit;
a differential circuit having the current mirror circuit as a load;
a first current source for supplying current to the differential circuit; first and second source follower circuits; and
a transistor for reset,
is characterized in that:
a first input signal is input through the first source follower circuit to the differential circuit;
a second input signal is input through the second source follower circuit to the differential circuit; and
during a period where voltage amplitude of an input signal is not converted, current supply by the first current source is blocked by a reset signal input to the transistor for reset.
According to an eighth aspect of the present invention, a level shifter for converting a signal having a low voltage amplitude into a signal having a high voltage amplitude and for outputting the converted signal, comprising:
a current mirror circuit;
a differential circuit having the current mirror circuit as a load;
a first current source for supplying current to the differential circuit;
first and second transistors, a gate electrode and a drain region of the first transistor being electrically connected to each other and a gate electrode and a drain region of the second transistor being electrically connected to each other; and
second and third current sources for supplying current to the first and second transistors, respectively,
is characterized in that:
a first input signal is input through the first transistor to the differential circuit;
a second input signal is input through the second transistor to the differential circuit; and
during a period where voltage amplitude of an input signal is not converted, current supply by the first, second, and third current sources is blocked.
According to a ninth aspect of the present invention, a level shifter for converting a signal having a low voltage amplitude into a signal having a high voltage amplitude and for outputting the converted signal, comprising:
a first transistor of a first conductive type, a gate electrode and a drain region thereof being connected to each other;
a second transistor of the first conductive type, a gate electrode and a drain region thereof being connected to each other;
a differential circuit comprising a third transistor of the first conductive type and a fourth transistor of the first conductive type;
a current mirror circuit comprising a fifth transistor of a second conductive type and a sixth transistor of the second conductive type, a gate electrode and a drain region of the fifth transistor being connected to each other;
a seventh transistor of the first conductive type for connecting the differential circuit and a first current source;
an eighth transistor of the second conductive type for electrically connecting the fifth transistor and a second current source;
a ninth transistor of the second conductive type for electrically connecting the sixth transistor and a third current source;
a power supply portion for supplying potential to gate electrodes of the seventh, eighth, and ninth transistors;
a first transistor for reset of the second conductive type; and
a second transistor for reset of the first conductive type,
is characterized in that:
a drain region of the first transistor and a gate electrode of the third transistor are electrically connected to each other;
a drain region of the second transistor and a gate electrode of the fourth transistor are electrically connected to each other;
a source region of the first transistor for reset is electrically connected to source regions of the seventh and eighth transistors, and a drain region of the first transistor for reset is electrically connected to gate electrodes of the seventh and eighth transistors;
a source region of the second transistor for reset is electrically connected to a source region of the ninth transistor, and a drain region of the second transistor for reset is electrically connected to a gate electrode of the ninth transistor;
a first input signal is input through the first transistor to the gate electrode of the third transistor;
a second input signal is input through the second transistor to the gate electrode of the fourth transistor; and
during a period where voltage amplitude of an input signal is not converted, current supply is blocked by a reset signal input to the first and second transistors for reset, and by making the seventh, eighth, and ninth transistors in a nonconductive state.
According to a tenth aspect of the present invention, a level shifter is characterized in that the first input signal is a signal having a low voltage amplitude, and the second input signal is a signal having a low voltage amplitude and in an opposite phase to that of the first input signal.
According to an eleventh aspect of the present invention, a level shifter is characterized in that the first input signal is a signal having a low voltage amplitude and the second input signal is a signal having a constant potential in a range of the amplitude of the first input signal.
According to a twelfth aspect of the present invention, a level shifter is characterized in that voltage amplitude of the input signal is 5V or lower.